1. Field of the Invention
The present invention relates to field-effect transistors and semiconductor devices including field-effect transistors. In particular, the present invention relates to a field-effect transistor whose threshold voltage is accurately settable and a semiconductor device including such a field-effect transistor.
2. Description of the Related Art
Mobile communication systems, for example, mobile phones and personal digital assistants (PDAs), send and receive high-frequency signals with microwave, monolithic integrated circuits (MMICs).
High-value-added MMICs, for example, switching integrated circuits (switching ICs) with built-in digital control circuits and switching integrated circuits with built-in logic circuits, are required.
Switching ICs include a depletion-mode field-effect transistor (DFET) and an enhancement-mode field-effect transistor (EFET) formed on the same substrate, the DFET and the EFET having different threshold voltages from each other.
Japanese Unexamined Patent Application No. 2-148740 discloses the following: To form a semiconductor device including a DFET and an EFET on the same substrate, the DFET and the EFET having different threshold voltages from each other, gate contact layers are formed on regions for forming the DFET and the EFET. Then, only the gate contact layer formed in the region for forming the EFET is etched to decrease the thickness of the gate contact layer, whereby the distance between the gate electrode of the EFET and the carrier supply layer of the EFET is shorter than that between the gate electrode of the DFET and the carrier supply layer of the DFET; consequently, the EFET and the DFET have different threshold voltages from each other.
Referring to FIG. 9, a buffer layer 112 composed of undoped gallium arsenide (GaAs), a channel layer 113 composed of undoped GaAs, and a barrier layer 114 composed of aluminum gallium arsenide (AlGaAs) are formed in that order on a GaAs semi-insulating substrate 111 by epitaxial growth to prepare a semiconductor device 119 including a DFET 120 and an EFET 121.
The barrier layer 114 includes a spacer sublayer 114a composed of AlGaAs, an electron supply sublayer 114b composed of AlGaAs doped with n-type impurities, and a gate contact sublayer 114c composed of undoped AlGaAs, formed in that order.
A masking layer composed of a resist is formed on the uppermost layer of the GaAs semi-insulating substrate 111. The barrier layer 114, the channel layer 113, and the buffer layer 112, which are formed in regions except a DFET-forming region and an EFET-forming region, are then etched, whereby the DFET and the EFET are isolated from each other. An insulating layer 115 is then formed on the GaAs semi-insulating substrate 111.
Gate apertures 115a and 115b are formed by etching the insulating layer 115 disposed in the regions for forming the DFET 120 and the EFET 121, in order to form embedded gate regions 114d and 114e. 
The gate aperture 115a in the region for forming the DFET 120 is masked with an appropriate resist layer, and then the gate contact sublayer 114c is etched through the gate aperture 115b in the region for forming the EFET 121, whereby the thickness of only the gate contact sublayer 114c in the region for forming the EFET 121 decreases.
The resist layer masking the gate aperture 115a in the region for forming the DFET 120 is removed, and then the embedded gate regions 114d and the 114e are formed by diffusing impurities into the gate contact sublayers 114c through the gate apertures 115a and 115b. 
Gate electrodes 118a and 118b are formed, and then source electrodes 116a and 116b and drain electrodes 117a and 117b are formed to prepare the DFET 120 and the EFET 121 simultaneously.